Broadcom Corporation
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Irvine,
CA
Broadcom's AirForce™ product family offers the broadest line of Wi-Fi® integrated circuits in the industry for system designs ranging from PC and consumer devices to access points and routers. Broadcom's AirForce™ 802.11a, 802.11b, 54g® and Intensi-fi® solutions enable manufacturers to build Wi-Fi products with the performance, interoperability, security and ease-of-use that consumers and businesses demand. AirForce solutions can be found in leading brands of Wi-Fi gear such as Apple, Belkin, Buffalo, Dell, eMachines, Gateway, HP, Linksys/Cisco, and Motorola.
Use Synopsis Primetime to generate .lib timing models of radio IP blocks. Verify design meets handoff requirements and work with the backend teams in the use and improvement of the model.
Serve as back up in the generation and verification of Verilog models of the radio and radio blocks. A strong background in Verilog and Verilog simulators is required.
Since tool flow is highly automated the applicant must also be strong in UNIX tools such as Makefiles, sed, awk, and grep. Finally, the applicant must also demonstrate a high level of ability in scripting languages such as Tcl and Python.
Job Requirements : • Typically requires a BS degree and 6 years of experience, an MS degree and 3 years of experience or a PhD and no experience.
• Strong programming skills in scripting languages such as Python, TCL, and Perl
• Strong knowledge of UNIX such as Makefiles, awk, sed, and grep
• Strong analytical, and problem solving skills as well as hands-on lab debugging skills.
• Solid understanding of version control and bug tracking systems such as CVS, SVN, and Gnats
• Knowledge of Verilog and Verilog simulators such as VCS, ncsim, and ModelSim
• Experience with timing tools and timing models like PrimeTime
WCG8144
City : Irvine
State : California
Country : United States
Irvine, California
Irvine, CA
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