Broadcom Corporation
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San Jose,
CA
-Design and develop custom advanced wirebond and flipchip packages substrate/module with supporting data including characterization, qualification, production readiness, cost effectiveness, and reliability
-Ensure package design follow SI constrains for cross-talk, IR drop, and noise in device. Ensure package solution meet device thermal performance requirement
-Work closely with both silicon design engineers and PCB layout designers to conduct feasibility studies and define flip chip bump patterns, wire-bond pad rings, as well as package ballout that achieve performance requirement with the lowest system total cost solution
-Define Assy process, troubleshoot and provide sustaining support on packaging issues. Consult on packaging problems & improvement in packaging process
-Work with marketing and chip lead to select packages and define packaging cost and roadmap for new devices
-New packaging and process technology development and deployment of the technology in HVM
-Work closely with QA and customer to resolve quality issues
-Interface with packaging vendors to identify quality, production and technology capabilities, technology improvement plans and cost reduction goals
Job Requirements : BS/MS/Phd in EE/ME/Physics/Material Science plus 7 + years experience with IC Package Design and Layout
Strong authority on package design processes and tools including APD/APE, UPD, ACAD for custom substrate and module design
Manufacturing processes experience on assembly of wirebond and flip chip packages, wafer bumping, wafer-level packaging, substrate manufacturing, and material selection is required
Solid background on FA and material characterization are required
Must have good oral communication and organization skills
City : San Jose
State : California
Country : United States
San Jose, California
San Jose, CA
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