Broadcom Corporation
-
Irvine,
CA
Design for test engineer lead/manager position. The position requires an energetic, proactive, self-starting person, who is able to coordinate/manage test engineering resources across & within teams. The person must possess strong technical knowledge in the area of design-for-test (DFT).
Job Description:
Design for Test Engineer to perform any of the following ASIC design tasks:
- Plan/coordinate/manage DFT resources on all design programs
- Develop best in class, highest quality DFT methodologies for all design teams in meeting all test requirements & silicon quality standards
- Implement/design/validate all DFT RTL/IP, required by all designs.
- Drive latest DFT tools to produces highest quality DFT RTL/IP.
- Drive ATPG generation/validation.
- Work with RTL design, test engineering teams to implement highest quality DFT implementation.
- Verify chip design for all DFT requirements, this includes DFT functional verification, DFT coverage verification and static timing analysis.
- Static Timing/Noise/Coupling Analysis.
- Generating clear documentation & easy to use scripts to support DFT flows.
- Evaluation of tools in the development of DFT flows.
- Responsible for day to day coordination of DFT design activity and resources, in meeting project schedules.
Job Requirements : Job Requirements:
Candidate must possess the following skills:
- ASIC design & implementation experience with specific background in the areas of Design for Test, RTL design & verification, static timing analysis, tool flow methodology (in order of priority.
- Minimum 12 years of experience with MSEE or 8 years with PHD.
- Must have at least 3 years experience in directly managing resources.
- Hands on experience with the following areas:
Logic Bist, Memory Bist, Boundary Scan, scan/ATPG design implementation
DFT process/flow development experience
Understanding of static timing and crosstalk/noise analysis.
Understanding of synthesis/timing closure concepts.
Write and read RTL in Verilog and/or VHDL.
Coding in scripting languages such as TCL, Perl and UNIX shell.
- Hands on experience with following layout design tools (in order of priority):
DFT: DFT Compiler, LogicVision*, TetraMAX, Fastscan, TestKompress
Lint: Spyglass*, NLINT
Synthesis: Design Compiler*
Static timing: Primetime*
Noise analysis: Celtic*, Primetime-SI
* indicates the preferred tools
City : Irvine
State : California
Country : United States
Irvine, California
Irvine, CA
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