Broadcom Corporation
-
Irvine,
CA
GigE Controller Verification team is in need of a Principal design verification engineer who enjoys working in a dynamic and fast-pace environment. A successful candidate will be working with the LSI design team to come up with verification strategies, develop test benches, develop test plans, implement test cases, provide test audits such as code coverage and functional coverage, and provide release documentations to end users.
The Candidate’s primary job functions will be to work with the LSI design team to do the following:
o Come up with Verification Strategies/architecture.
o Develop verification test benches with HVL (i.e. Specman and/or SystemVerilog)
o Develop Test plans from design specifications and Standards documentations
o Implement test cases outlined in test plans
o Provide test audit report of code coverage and functional coverage
o Hold design reviews with LSI designers.
o Understand and implement ABV (Assertion Based Verification).
o Understand VMM/OVL methodologies
Job Requirements : We are looking for an engineer who:
1) Enjoys technical challenges and promptly comes to resolution.
2) Understands the dynamic nature of engineering and accommodates by working under flexible hour arrangements (i.e. normal day shift and/or late hours at times).
3) Understands the concept of teamwork and does not make a distinction in assignment boundaries. In other words, one who goes beyond his/her assignments to help meet project objectives.
4) Is confident enough to challenge managers and or chip leads on decisions that would compromise project objectives.
5) Has diverse knowledge in the area of design verification and applying the knowledge on real designs. These include, but are not limited to, understanding the tradeoff of different verification solutions (i.e. block sims vs. chip sims., Verilog vs. HVL like Specman or Vera, etc.), working knowledge with various verification tools (i.e. Specman, NC-sim, System Verilog, Debussy, etc.), writing scripts to automate verification process (i.e. using Make, TCL, PERL, etc.), debugging RTL/gate-level netlist to resolve issues, understand assertion languages (i.e. SVA, PSL, etc.), implement tests to trigger the assertions, and generating test vectors for ATE engineers.
6) Has several years (i.e. minimum of 12 yrs) of directly working as a design verification engineer performing similar tasks outlined in #5 above. However, if you feel you have the competency in executing those tasks but lack the minimum years of experience, you are encouraged to still apply since "competency" is the key factor not necessary "years of experience."
7) Has lead/supervised a small team of 2 or more.
8) Self driven and can execute tasks with high level objectives.
9) Understand protocols such as PCI-Express, Ethernet, AHB, AXI is a plus.
City : Irvine
State : California
Country : United States
Irvine, California
Irvine, CA
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